1. Field of the Invention
The present invention relates to an image pickup apparatus having an image pickup device and a control method therefor, and more particular, to an image pickup apparatus having a solid-state image pickup device with A/D converters, such as a complementary metal oxide semiconductor image sensor (hereinafter, referred to as the CMOS sensor), and a control method therefor.
2. Description of the Related Art
With integration of a CMOS logic process and an image sensor process, it becomes possible to mount analog circuits, digital circuits, signal processors, etc. onto a chip of a solid-state image pickup device such as a CMOS sensor. For example, a CMOS sensor has already come into practical use that has an image sensor chip on which pixels are two-dimensionally arranged and A/D converters are mounted.
In a CMOS sensor of this type, a column parallel A/D conversion architecture is used, in which A/D converters are each provided for a corresponding one of columns of two-dimensionally arranged pixels, whereby a conversion rate in each A/D converter can be lowered from a pixel readout rate to a line readout rate. This is advantageous in that the entire power consumption can be reduced and the readout rate of the CMOS sensor can easily be increased.
As the CMOS sensor using the column parallel A/D conversion architecture, a CMOS sensor using so-called ramp type A/D converters with triangle-wave sweep has been known (see, for example, Japanese Laid-open Patent Publication No. H5-48460).
In this CMOS sensor, analog values input from analog value input terminals are stored into an analog value storage unit, and these analog values are input to respective one input terminals of comparators, whereas reference values from D/A converters gradually increasing with a counter operation are input to respective other input terminals of the comparators. When each of the analog values becomes smaller than the corresponding reference value, counter data is stored into a digital value storage unit. Subsequently, pieces of counter data are read as digital values in sequence from the digital value storage unit by a scanning circuit.
As previously described, the reference values (i.e., triangle waves) are applied to the comparators of the CMOS sensor. In a case, for example, that the CMOS sensor is mounted with 8-bit A/D counters, a time period for performing 256-step processing (where 256 is 2 raised to the eighth power) is required to sweep the triangle wave so as to change the voltage of the triangle wave in synchronism with a counter operation.
The triangle wave is supplied in the form of analog voltage, and a time period required for the triangle wave to be stabilized is determined according to an RC time constant. It is therefore difficult in principle to shorten each step processing time to less than the time period required for the triangle wave to be stabilized.
In other words, the number of steps required to sweep the triangle wave increases with increase in the number of bits used in the A/D converters, which makes it difficult to increase the processing speed. With the CMOS sensor using ramp type A/D converters, it is therefore difficult to simultaneously satisfy the demand for increasing the number of bits of the A/D converters and the demand for increasing the processing speed.
Some of CMOS sensors using the column parallel A/D conversion architecture is configured to operate an n-bit counter in a mode for performing 2n-step counting to increase the number of bits of a ramp type A/D converter, or in a mode for counting of a less number of steps to increase the processing speed, while reducing the number of bits to less than n (see, for example, Japanese Laid-open Patent Publication No. 2005-333316). With this CMOS sensor, by selectively using one of these two operation modes, an object moving at a high speed can be photographed, and a photograph with smooth gradations can be taken.
With this CMOS sensor, however, in order to increase the processing speed, the number of bits must be reduced, so that the gradation representation becomes rough. In other words, even if either the operation mode attaching importance to the increase of the number of bits or the operation mode attaching importance to the increase of processing speed can be selected, it is difficult to simultaneously satisfy the demand for increasing the number of bits and the demand for increasing the processing speed.